(1) Field of the Invention
The present invention relates to a semiconductor recording device such as a memory card and a method of controlling the semiconductor recording device, and particularly relates to a control method of suppressing variation in data retention characteristics of a o nonvolatile memory and deterioration involved in frequent rewriting onto the semiconductor recording device.
(2) Description of the Related Art
Conventionally a semiconductor recording device such as a is Secure Digital (SD) card that is a card-type recording medium including a flash memory is a microminiature and super-slim recording medium widely used in a digital camera, a mobile device, and so on for recoding the data such as images.
The flash memory incorporated in the semiconductor recording device is a memory including multiple physical blocks of a predetermined size and allows erasing the data in units of physical blocks. In response to a demand for mass-storage that has been growing in recent years, a multivalued flash memory has been commercialized which allows accumulation of the data of 2 bits or more in one cell.
As an example of the multivalued flash memory, a four-value flash memory will be described with reference to FIG. 1. FIG. 1 is a diagram showing a relationship between an accumulation state of electrons accumulated in a floating gate of the four-value flash memory and a threshold voltage (Vth).
As shown in FIG. 1, the four-value flash memory controls such an accumulation state of electrons in the floating gate in four states according to the threshold voltage (Vth) thereof. In FIG. 1, a state which indicates a smallest number of accumulated electrons (charge amount of electrons) and thus indicates a lowest potential is an erase state represented as (1, 1). Subsequently, as more and more electrons are accumulated, the threshold voltage discretely increases, and the resulting statuses are represented as: (1, 0), (0, 0), and (0, 1), respectively. Thus, since the potential increases in proportion to the number of electrons accumulated, it is possible to control the accumulation state of the electrons in four states such that the potential falls within the predetermined potential threshold. This allows recording 2-bit data in one memory cell.
However, since the four-value flash memory distinguishes between the four states according to the amount of electron charge, a difference between the threshold voltage and each of the states of the four-value flash memory is smaller than the difference between the states and the threshold voltage of the two-value flash memory.
In addition, rewriting of data, when repeated, causes slight is damage to a gate oxide film as a result of injection and extraction of electrons. Such damages, when accumulated, form a number of electron traps, thus resulting in decrease in actual number of electrons to be accumulated in the floating gate. Furthermore, in proportion to miniaturization of semiconductor processing, the number of electrons accumulated in the floating gates is smaller; thus, further miniaturization of the flash memory results in a greater influence of the electron trap.
As described above, further miniaturization of the multivalued record and semiconductor process that support mass-storage of the flash memory has come to further highlight the problem of deterioration in data retention characteristics of the flash memory.
Adopted as methods to solve the above problem are (1) restricting the frequency of rewriting and (2) reinforcing error correction.
For example, Patent Reference 1 (Japanese Unexamined Patent Application Publication No. 2006-18373) discloses a technique of suppressing deterioration of data retention characteristics of the flash memory by reinforcing error correction ability by: in a flash memory including plural chips, associating blocks included in different chips within the flash memory with each other to treat the associated blocks as a common group, and assigning one block in the common group to a block for parity of user data written in another block in the common group.
However, the technique disclosed in Patent Reference 1 merely applies RAID 4 or RAID 5 that is used in HDD to the flash memory, but does not consider the configuration of the NAND-type flash memory. Thus, the method disclosed in Patent Reference 1 does not sufficiently allow suppressing deterioration of the data retention characteristics of the flash memory, thus causing a problem of occurrence of failure such as a read error.
The following will describe the problem with reference to FIG. 2. FIG. 2 is a diagram showing a memory cell configuration of the NAND-type flash memory.
As shown in FIG. 2, the NAND-type flash memory includes a matrix of flash memory cells. In a column direction, a plurality of flash memory cells directly connecting a source and a drain between a gate SGS on the source side and a gate SGB on the bit line side. In a row direction, a common word line is connected to a gate of each flash memory cell (corresponding to each page of the physical block), and a write operation or a read operation is simultaneously performed on the flash memory cells arranged along the word line.
In the write operation, a voltage Vdd is applied to a word line that is not selected, and a high voltage of approximately 20 V is applied to the word line of the flash memory that is selected, to thereby inject electrons into a floating gate of the flash memory cell into which the data is to be written.
In the read operation, the voltage Vdd is applied to the word line that is not selected, and a voltage of Vt (<Vdd) is applied to a word line of the flash memory cell that is selected. At this time, when electrons are injected into the flash memory cell in the selected word line, the flash memory turns on, and “0” is read via the bit line. On the other hand, when electrons are not injected into the flash memory cell in the selected word line, the flash memory turns off, and “1” is read via the bit line.
As the semiconductor process is more miniaturized, a smaller number of electrons are to be injected into the floating gate, which significantly increases an influence of variation in the number of electrons to be injected in each flash memory cell on the data retention characteristics. For example, an increase of some mV in the potential of the source of each flash memory cell decreases the number of electrons injected into the flash memory cell by an amount of some mV.
In the NAND-type flash memory, a flash memory that is provided in a word line located farther from the source line (reference potential line) is more affected by potential increase on the source side. For example, in FIG. 2, the flash memory cell located in word line WL7 that is farthest from the source line is most affected by potential increase on the source side.
Accordingly, in the NAND-type flash memory, a larger page number is more likely to result in further deterioration in data retention characteristics.
Thus, in improvement of data retention characteristics according to the technique disclosed in Patent Reference 1 using RAID configuration, no effective measure has been provided to deal with the structural characteristics of the NAND-type flash memory that the larger page number causes further deterioration of data retention characteristics; thus, there is a problem of being unable to sufficiently improve data retention characteristics as compared to the case of parity redundancy.